Thermal management of multi-chip electronic packages is critical to ideal performance of the multi-chip electronic packages and related electronic systems. Currently, multi-chip electronic packages encapsulate chips between a lid and chip carrier by forming a gap between pistons of the lid and the chips mounted on the chip carrier, and dispensing a thermal interface material (TIM) within the gap. The gap is formed by the use of a chip shim placed between each piston of the lid and a respective singe chip of the multi-chip electronic packages.
However, semiconductor chips are increasing in size due to requirements of incorporating increased functionality (e.g., logic and memory). This increase in semiconductor chip size together with the requirement to package multiple chips and decoupling capacitors on the same chip carrier lead to increasing chip carrier sizes and increasing costs. One solution to packaging multiple larger chips on the same chip carrier is to decrease the inter-chip spacing by restricting bond and assembly ground rules and cooling hardware changes. For example, FIG. 1a shows a space provided between the chips on the carrier, on the order of 1 millimeter to 2 millimeter spacing with, for example, passive components (e.g., capacitors), between the chips. Chip to chip spacings of <1 mm are possible if passive components are not required. These bond and assembly ground rule changes, though, can have undesirable consequences on the final product such as, for example, an increase in temperature of the chip.
More specifically, FIG. 1b shows a conventional chip package including a plurality of chips 12 attached to a chip carrier 10. A lid or hat 14 (hereinafter referred to as a lid) is positioned over the chip carrier 10, with thermal paste between each of the plurality of chips and a respective piston 16. As is known in the industry, the pistons 16 and thermal paste act as heat sinks, cooling the chips 12 during operation of the chips 12, e.g., in the final product such as, for example, a computer. In these conventional systems, only a single piston is provided for a single chip. However, as shown in FIG. 1b, the pistons 16 do not cover the entirety of the chip 12, leaving uncovered spaces at edges of the chip. This is mainly due to the fact that the pistons cannot have the same spacing as the chips which, in turn, leads to an increase in chip temperature.
More specifically, as should be understood, the plurality of chips and the pistons are not under the same spacing constraints. For example, in chip package design, it is possible to place the chips 12 on the carrier with a very narrow space therebetween, e.g., typically about 1 millimeter to 2 millimeters. However, this same spacing is not possible between the pistons while still maintaining the lid integrity. For example, utilizing a typical lid material of copper or aluminum, the spacing between the pistons on the lids has to be much larger, e.g., on the order of 4 to 5 millimeters, to ensure that the lid does not warp. For this reason, it is not possible for the each piston 16 to completely cover the surfaces of a respective chip 12, as a surface area of the piston must be smaller than a surface are of the chip due to the constrain on piston spacing. This results in an increase in temperature at the chips' edges.
FIG. 1c shows a graph of temperature vs. chip spacing using the conventional package of FIG. 1b. More specifically, FIG. 1c shows a significant increase of about 4° C. at the edges of the chips, which are uncovered. The temperature increase also affects the central area or core of the chips, e.g., with about a 2° C. increase in temperature. As should be understood by those of skill in the art, this temperature increase can affect performance of the chip package.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.